The present disclosure relates to producing interconnects in semiconductor devices. Such interconnects can be composed of selected metals and metal alloys deposited in workpiece features by electroplating and followed by thermal diffusion. Such interconnects can include selective metal caps placed over trenches or vias. Such interconnects can also include plating an etch stop over a via to create an alignment-tolerant via.
Integrated circuits (IC) include various semiconductor devices formed within or on layers of dielectric material that overlies a substrate. Such devices which may be formed in or on the dielectric layers include MRS transistors, bipolar transistors, diodes, and diffused resistors. Other devices which may be formed in or on the dielectric material include thin film resistors and capacitors. Metal lines interconnect the semiconductor devices to power such devices and enable such devices to share and exchange information. Such interconnects extend horizontally between devices within a dielectric layer as well as vertically between dielectric layers. These metal lines are connected to each other by a series of interconnects. The electrical interconnects or metal lines are first patterned into the dielectric layers to form vertical and horizontal recessed features (vias and trenches) that are subsequently filled with metal. The resulting layer containing metal-filled lines residing in a dielectric is referred to as a metallization layer.
Next, a second metallization layer is similarly formed on top of the first metallization layer and interconnects are formed between the two metallization layers. A stack containing several metallization layers which are electrically connected to each other by a plurality of interconnects can be formed using this process. This process is known as Damascene processing. Damascene processing typically employs copper (Cu) as the metallization metal. However, other metals may also be utilized, including aluminum (Al), cobalt (Co), Nickel (Ni), Gold (Au), Silver (Ag), Manganese (Mn), Tin (Sn), and alloys thereof.
The typical process of forming metal interconnections or lines, for example, from copper, requires several steps. Initially, vertical and horizontal features (vias and trenches) are patterned and formed in the dielectric substrate. Eventually the vias and trenches are filled with copper, but beforehand a barrier layer and a seed layer are applied to the feature. Because copper tends to diffuse into the dielectric material, barrier layers are used to isolate the copper deposit from the dielectric material. The diffusion of copper into the surrounding dielectric material would lead to line-to-line leakages and eventual failure of the semiconductor devices. As such, it is common to fully enclose or encapsulate copper lines with a diffusion barrier. However, if other metals are used for metallization, it is to be appreciated that barrier layers may not be needed. Barrier layers are typically made from refractory metals or refractory compounds, for example, titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), etc. The barrier layer is commonly formed using a deposition technique called physical vapor deposition (PVD), but may also be formed using other deposition techniques, such as chemical vapor deposition (CVD) or atomic layer deposition (ALD).
A seed layer can be deposited on the barrier layer. The purpose of the seed layer can be: to provide a low-resistance electrical path which enables more uniform electrical plating over the barrier layer; and/or to assist the copper or other trench or via material to adhere well to the barrier layer, thereby to provide a continuous platable film to plate on. As such, the seed layer can be composed of a copper or copper alloy, such as copper manganese, copper cobalt, or copper nickel. The seed layer can also be composed of aluminum or an aluminum alloy. Also, various options exist for depositing a seed layer, such as using PVD for copper seed layer deposition. The seed layer may also be formed by using other deposition techniques, such as CVD or ALD.
The seed layer can be a stack film, for example, a liner layer and a PVD seed layer. A liner layer is a material used on a barrier layer or between a barrier layer and a PVD seed layer to mitigate discontinuous seed issues and improve adhesion of the PVD seed to the barrier layer. Liner layers are typically composed of noble metals, such as ruthenium (Ru), platinum (Pt), palladium (Pd), and osmium (Os). Liners can also be composed of Co or Ni. Currently, CVD Ru and CVD Co are commonly used to create liners; however, liner layers may also be formed by using other deposition techniques, including ALD or PVD.
The seed layer can also be a secondary seed layer, which is similar to a liner layer in that it is typically formed from noble metals, such as Ru, Pt, Pd, or Os. However, other materials may be utilized, including Co and Ni, and also commonly CVD Ru and CVD Co. As in seed and liner layers, secondary seed layers may also be formed using ALD, PVD, or other deposition techniques. A secondary seed layer differs from the liner layer in that the secondary seed layer actually serves as the seed layer, whereas the liner layer is an intermediate layer between the barrier layer and the PVD seed layer.
After the seed layer has been deposited, the feature may be filled with copper using, for example, electrochemical deposition under acid deposition chemistry (“ECD”). Conventional ECD copper acid chemistry may include, for example, copper sulfate, sulfuric acid, hydrochloric acid, and organic additives (such as accelerators, suppressors, and levelers). Electrochemical deposition of copper has been found to be a cost effective manner by which to deposit a copper metallization layer. In addition to being economically viable, ECD techniques provide a substantially “bottom up” (e.g., nonconformal) metal fill that is mechanically and electrically suitable for interconnected structures.
A long-standing objective in the advancement of IC technology has been the scaling down of IC dimensions. Such scaling-down of IC dimensions is critical to obtaining higher speed performance of ICs. An increase in IC performance is normally accompanied by a decrease in device area and/or an increase in device density. An increase in device density requires a decrease in via and trench dimensions (widths) used to form the interconnects. However, as feature dimensions on wafers decrease, negative consequences can come to bear. For example, reduced-size features may result in less reliable interconnects.
A conventional copper fill to produce interconnects can result in voids, particularly in features having a size of less than 30 nm. As one example of a type of void formed using conventional copper deposition, the opening of the feature may pinch off. Other types of voids can also result from using conventional copper fill process in small features. Such voids and other intrinsic properties of a deposit formed using conventional copper fill techniques can increase the resistance of the interconnect, thereby slowing down electrical performance of the device and reducing the reliability of the copper interconnect.
A further result of the ever-decreasing scaling down of interconnects is electromigration failure. Electromigration redistributes the copper in the interconnect and creates extrusions that can expand into the dielectric space. Generally, electromigration occurs when the metal atoms of conductive lines are subjected to high current density when the circuit is in operation. Metal atoms migrate in the direction of electron flow if the current density is high enough, thereby forming voids where metal ions have departed and forming extrusions consisting of metal material protruding outside the metal or dielectric barrier along the length of the metal interconnect. Voids will cause the copper interconnect to thin out and eventually separate completely, causing an open circuit. Moreover, extrusions can cause the copper metal to extend past the copper interconnect and into an adjacent copper line, thereby causing a short circuit.
With increasing miniaturization of integrated circuits, the likelihood of failure of interconnects due to electromigration increases with copper interconnects, because failure is caused by smaller voids. This necessitates a remedy to electromigration failures.
Once a void begins to develop in a metal line, the conducting metal becomes narrower at that point. Due to the reduction in conductor cross section, current density through the line increases at the narrowed location. As a result, the interconnect temperature increases due to Joule heating. As the temperature of the interconnect rises, the growth of the void accelerates, leading to a vicious cycle that eventually results in an open circuit.
One solution to reducing or minimizing electromigration is to apply a metal cap over the copper fill. However, the process of producing the metal cap can be time-consuming and expensive. Perhaps more importantly, in existing methods for producing a metal cap, metal residue can remain that extends between the metal lines, eventually causing a short circuit or other failure to occur.
In one method of forming a metal cap, after a metal liner has been deposited on the sidewalls and bottom surface of a feature, the metal layer is electroplated on the metal liner to fill the feature with, for example, copper. Typically, the metal layer overlies the dielectric layer in which the feature exists. As such, it is necessary to planarize the metal lining to be coextensive with the top layer of the dielectric surface. This can be carried out by, for example, chemical mechanical polishing (CMP). As a result, the top surface of the metal layer is now substantially coplanar with the dielectric layer top surface.
Next the metal line is recessed below the level of the dielectric layer top surface by an etching process selective to the metal liner and the dielectric layer. In this manner, the amount of removal of the metal liner and dielectric layer is insignificant relative to the removal of material from the surface of the metal line. Next, a cap layer is deposited over the recessed surface of the metal line as well as over the top edges of the sidewalls of the metal liner and over the dielectric layer top surface. Typically, the thickness of the cap layer is from about 5 nm to about 100 nm, but more commonly from about 12 nm to about 50 nm. Next, a further planarization process is carried out so that the top surface of the cap is coextensive with the top surface of the dielectric layer.
In another process for achieving a metal cap on copper or other conductor used for interconnects, after the copper is otherwise plated or deposited into the feature formed in the dielectric material, the wafer is planarized, for example, by CMP processing. Thereafter Next, a further thin dielectric cap is formed over the metal blanket film. Next, a photoresist coating is deposited over the thin dielectric cap, and a lithographic exposure process is performed using a lithographic mask. In this manner, the Ta/TaN metal cap between the copper lines is etched away, leaving the metal cap only over the copper lines. However, in this process, not uncommonly, a residue may be left between the copper lines, which could eventually result in shorting the lines, or other reliability problems, especially as the lines become thinner and thinner.
One way, of course, of addressing the drawbacks of copper metallization is to use a copper alloy or a metal other than copper, for example, Co, Ni, Mn, Sn, Au, Ag, Al, or alloys thereof. Plating or otherwise depositing these metals in small features can, as in plating copper, result in low quality interconnects due to the formation of defects including voids. These voids, as noted above, can reduce the performance of the semiconductor circuit and also reduce the reliability of the metal interconnect.
Another consequence of increasing the density of IC device density is that it becomes more difficult to avoid interconnects in adjacent semiconductor layers. As a consequence, when locating semiconductor devices and/or features for interconnects, it is difficult to void interconnects on a pre-existing layer. It would be desirable if alignment-tolerant vias could be incorporated into interconnects.
The present invention is intended to address the foregoing issues, as well as provide improved performance and reliability of interconnects used in semiconductor manufacturing.